This paper/link talks about resnet's bottleneck design.
It's totally not clear to me how the bottleneck design on the right is equivalent to the left-diagram and how is it reducing the parameters? Left has 64-d input whereas right has 256-d. What is 'd' denote? If it's channel in the input, then what does 64 in '1x1, 64' denote? If the input to 1x1 conv is 256 channel, then doesn't it implicity mean, we have a filter of 1x1x256 for the conv? So not sure, where that 64 comes from.
In short it's very unclear how left-side is equivalent to the bottneck diagram on right and how right is better. Could someone please explain?